RTE_Device.h File Reference

Go to the source code of this file.

## Macros

#define | RTE_USB_USB0 0
#define | RTE_USB_PPWR_ID 1
#define | RTE_USB_PPWR_PIN_EN 1
#define | RTE_USB_PWRD_ID 1
#define | RTE_USB_PWRD_PIN_EN 1
#define | RTE_USB_OVRCR_ID 0
#define | RTE_USB_OVRCR_PIN_EN 0
#define | RTE_USB_CONNECT_ID 1
#define | RTE_USB_CONNECT_PIN_EN 1
#define | RTE_USB_VBUS_ID 1
#define | RTE_USB_VBUS_PIN_EN 1
#define | RTE_USB_UP_LED_ID 1
#define | RTE_USB_UP_LED_PIN_EN 1
#define | RTE_ENET 0
#define | RTE_ENET_RMII 1
#define | RTE_ENET_RMII_TXD0_PORT_ID 0
#define | RTE_ENET_RMII_TXD0_PORT 1
#define | RTE_ENET_RMII_TXD0_PIN 0
#define | RTE_ENET_RMII_TXD0_FUNC 1
#define | RTE_ENET_RMII_TXD1_PORT_ID 0
#define | RTE_ENET_RMII_TXD1_PORT 1
#define | RTE_ENET_RMII_TXD1_PIN 1
#define | RTE_ENET_RMII_TXD1_FUNC 1
#define | RTE_ENET_RMII_REF_CLK_PORT_ID 0
#define | RTE_ENET_RMII_REF_CLK_PORT 1
#define | RTE_ENET_RMII_REF_CLK_PIN 15
#define | RTE_ENET_RMII_REF_CLK_FUNC 1
#define | RTE_ENET_RMII_TX_EN_PORT_ID 0
#define | RTE_ENET_RMII_TX_EN_PORT 1
#define | RTE_ENET_RMII_TX_EN_PIN 4
#define | RTE_ENET_RMII_TX_EN_FUNC 1
#define | RTE_ENET_RMII_CRS_PORT_ID 0
#define | RTE_ENET_RMII_CRS_PORT 1
#define | RTE_ENET_RMII_CRS_PIN 8
#define | RTE_ENET_RMII_CRS_FUNC 1
#define | RTE_ENET_RMII_RXD0_PORT_ID 0
#define | RTE_ENET_RMII_RXD0_PORT 1
#define | RTE_ENET_RMII_RXD0_PIN 9
#define | RTE_ENET_RMII_RXD0_FUNC 1
#define | RTE_ENET_RMII_RXD1_PORT_ID 0
#define | RTE_ENET_RMII_RXD1_PORT 1
#define | RTE_ENET_RMII_RXD1_PIN 10
#define | RTE_ENET_RMII_RXD1_FUNC 1
#define | RTE_ENET_RMII_RX_ER_PORT_ID 0
#define | RTE_ENET_RMII_RX_ER_PORT 1
#define | RTE_ENET_RMII_RX_ER_PIN 14
#define | RTE_ENET_RMII_RX_ER_FUNC 1
#define | RTE_ENET_MDI_MDC_PORT_ID 0
#define | RTE_ENET_MDI_MDC_PORT 1
#define | RTE_ENET_MDI_MDC_PIN 16
#define | RTE_ENET_MDI_MDC_FUNC 1
#define | RTE_ENET_MDI_MDIO_PORT_ID 0
#define | RTE_ENET_MDI_MDIO_PORT 1
#define | RTE_ENET_MDI_MDIO_PIN 17
#define | RTE_ENET_MDI_MDIO_FUNC 1
#define | RTE_I2C0 0
#define | RTE_I2C0_SCL_PORT_ID 0
#define | RTE_I2C0_SCL_PORT 0
#define | RTE_I2C0_SCL_PIN 28
#define | RTE_I2C0_SCL_FUNC 1
#define | RTE_I2C0_SDA_PORT_ID 0
#define | RTE_I2C0_SDA_PORT 0
#define | RTE_I2C0_SDA_PIN 27
#define | RTE_I2C0_SDA_FUNC 1
#define | RTE_I2C1 0
#define | RTE_I2C1_SCL_PORT_ID 0
#define | RTE_I2C1_SCL_PORT 0
#define | RTE_I2C1_SCL_PIN 1
#define | RTE_I2C1_SCL_FUNC 3
#define | RTE_I2C1_SDA_PORT_ID 0
#define | RTE_I2C1_SDA_PORT 0
#define | RTE_I2C1_SDA_PIN 0
#define | RTE_I2C1_SDA_FUNC 3
#define | RTE_I2C2 1
#define | RTE_I2C2_SCL_PORT_ID 0
#define | RTE_I2C2_SCL_PORT 0
#define | RTE_I2C2_SCL_PIN 11
#define | RTE_I2C2_SCL_FUNC 2
#define | RTE_I2C2_SDA_PORT_ID 0
#define | RTE_I2C2_SDA_PORT 0
#define | RTE_I2C2_SDA_PIN 10
#define | RTE_I2C2_SDA_FUNC 2
#define | RTE_UART0 0
#define | RTE_UART0_TX_ID 0
#define | RTE_UART0_TX_PIN_EN 0
#define | RTE_UART0_RX_ID 0
#define | RTE_UART0_RX_PIN_EN 0
#define | RTE_UART0_DMA_TX_EN 1
#define | RTE_UART0_DMA_TX_CH 0
#define | RTE_UART0_DMA_RX_EN 1
#define | RTE_UART0_DMA_RX_CH 1
#define | RTE_UART1 0
#define | RTE_UART1_TX_ID 1
#define | RTE_UART1_TX_PORT 0
#define | RTE_UART1_TX_BIT 15
#define | RTE_UART1_TX_FUNC 1
#define | RTE_UART1_TX_PIN_EN 1
#define | RTE_UART1_RX_ID 1
#define | RTE_UART1_RX_PORT 0
#define | RTE_UART1_RX_BIT 16
#define | RTE_UART1_RX_FUNC 1
#define | RTE_UART1_RX_PIN_EN 1
#define | RTE_UART1_CTS_ID 0
#define | RTE_UART1_CTS_PIN_EN 0
#define | RTE_UART1_DCD_ID 0
#define | RTE_UART1_DCD_PIN_EN 0
#define | RTE_UART1_DSR_ID 0
#define | RTE_UART1_DSR_PIN_EN 0
#define | RTE_UART1_DTR_ID 0
#define | RTE_UART1_DTR_PIN_EN 0
#define | RTE_UART1_RI_ID 0
#define | RTE_UART1_RI_PIN_EN 0
#define | RTE_UART1_RTS_ID 0
#define | RTE_UART1_RTS_PIN_EN 0
#define | RTE_UART1_DMA_TX_EN 1
#define | RTE_UART1_DMA_TX_CH 0
#define | RTE_UART1_DMA_RX_EN 1
#define | RTE_UART1_DMA_RX_CH 1
#define | RTE_UART2 0
#define | RTE_UART2_TX_ID 0
#define | RTE_UART2_TX_PIN_EN 0
#define | RTE_UART2_RX_ID 0
#define | RTE_UART2_RX_PIN_EN 0
#define | RTE_UART2_DMA_TX_EN 1
#define | RTE_UART2_DMA_TX_CH 0
#define | RTE_UART2_DMA_RX_EN 1
#define | RTE_UART2_DMA_RX_CH 1
#define | RTE_UART3 0
#define | RTE_UART3_TX_ID 0
#define | RTE_UART3_TX_PIN_EN 0
#define | RTE_UART3_RX_ID 0
#define | RTE_UART3_RX_PIN_EN 0
#define | RTE_UART3_DMA_TX_EN 1
#define | RTE_UART3_DMA_TX_CH 0
#define | RTE_UART3_DMA_RX_EN 1
#define | RTE_UART3_DMA_RX_CH 1
#define | RTE_CAN_CAN1 0
#define | RTE_CAN1_RD_ID 0
#define | RTE_CAN1_RD_PIN_EN 0
#define | RTE_CAN1_TD_ID 0
#define | RTE_CAN1_TD_PIN_EN 0
#define | RTE_CAN_CAN2 1
#define | RTE_CAN2_RD_ID 0
#define | RTE_CAN2_RD_PIN_EN 0
#define | RTE_CAN2_TD_ID 0
#define | RTE_CAN2_TD_PIN_EN 0
#define | RTE_SSP0 1
#define | RTE_SSP0_SSEL_PIN_SEL 1
#define | RTE_SSP0_SSEL_PORT 0
#define | RTE_SSP0_SSEL_BIT 16
#define | RTE_SSP0_SSEL_FUNC 2
#define | RTE_SSP0_SSEL_PIN_EN 1
#define | RTE_SSP0_SCK_PIN_SEL 0
#define | RTE_SSP0_SCK_PORT 0
#define | RTE_SSP0_SCK_BIT 15
#define | RTE_SSP0_SCK_FUNC 2
#define | RTE_SSP0_MISO_PIN_SEL 1
#define | RTE_SSP0_MISO_PORT 0
#define | RTE_SSP0_MISO_BIT 17
#define | RTE_SSP0_MISO_FUNC 2
#define | RTE_SSP0_MISO_PIN_EN 1
#define | RTE_SSP0_MOSI_PIN_SEL 1
#define | RTE_SSP0_MOSI_PORT 0
#define | RTE_SSP0_MOSI_BIT 18
#define | RTE_SSP0_MOSI_FUNC 2
#define | RTE_SSP0_MOSI_PIN_EN 1
#define | RTE_SSP0_DMA_TX_EN 0
#define | RTE_SSP0_DMA_TX_CH 0
#define | RTE_SSP0_DMA_RX_EN 0
#define | RTE_SSP0_DMA_RX_CH 1
#define | RTE_SSP1 1
#define | RTE_SSP1_SSEL_PIN_SEL 1
#define | RTE_SSP1_SSEL_PORT 0
#define | RTE_SSP1_SSEL_BIT 6
#define | RTE_SSP1_SSEL_FUNC 2
#define | RTE_SSP1_SSEL_PIN_EN 1
#define | RTE_SSP1_SCK_PIN_SEL 0
#define | RTE_SSP1_SCK_PORT 0
#define | RTE_SSP1_SCK_BIT 7
#define | RTE_SSP1_SCK_FUNC 2
#define | RTE_SSP1_MISO_PIN_SEL 1
#define | RTE_SSP1_MISO_PORT 0
#define | RTE_SSP1_MISO_BIT 8
#define | RTE_SSP1_MISO_FUNC 2
#define | RTE_SSP1_MISO_PIN_EN 1
#define | RTE_SSP1_MOSI_PIN_SEL 1
#define | RTE_SSP1_MOSI_PORT 0
#define | RTE_SSP1_MOSI_BIT 9
#define | RTE_SSP1_MOSI_FUNC 2
#define | RTE_SSP1_MOSI_PIN_EN 1
#define | RTE_SSP1_DMA_TX_EN 0
#define | RTE_SSP1_DMA_TX_CH 2
#define | RTE_SSP1_DMA_RX_EN 0
#define | RTE_SSP1_DMA_RX_CH 3
#define | RTE_SPI 1
#define | RTE_SPI_SSEL_PIN_SEL 1
#define | RTE_SPI_SSEL_PORT 0
#define | RTE_SPI_SSEL_BIT 16
#define | RTE_SPI_SSEL_FUNC 3
#define | RTE_SPI_SSEL_PIN_EN 1
#define | RTE_SPI_SCK_PIN_SEL 0
#define | RTE_SPI_SCK_PORT 0
#define | RTE_SPI_SCK_BIT 15
#define | RTE_SPI_SCK_FUNC 3
#define | RTE_SPI_MISO_PIN_SEL 1
#define | RTE_SPI_MISO_PORT 0
#define | RTE_SPI_MISO_BIT 17
#define | RTE_SPI_MISO_FUNC 3
#define | RTE_SPI_MISO_PIN_EN 1
#define | RTE_SPI_MOSI_PIN_SEL 1
#define | RTE_SPI_MOSI_PORT 0
#define | RTE_SPI_MOSI_BIT 18
#define | RTE_SPI_MOSI_FUNC 3
#define | RTE_SPI_MOSI_PIN_EN 1
#define | RTE_I2S0 0
#define | RTE_I2S0_RX_SCK_PIN_SEL 1
#define | RTE_I2S0_RX_SCK_PORT 0
#define | RTE_I2S0_RX_SCK_BIT 4
#define | RTE_I2S0_RX_SCK_FUNC 1
#define | RTE_I2S0_RX_SCK_PIN_EN 1
#define | RTE_I2S0_RX_WS_PIN_SEL 1
#define | RTE_I2S0_RX_WS_PORT 0
#define | RTE_I2S0_RX_WS_BIT 5
#define | RTE_I2S0_RX_WS_FUNC 1
#define | RTE_I2S0_RX_WS_PIN_EN 1
#define | RTE_I2S0_RX_SDA_PIN_SEL 1
#define | RTE_I2S0_RX_SDA_PORT 0
#define | RTE_I2S0_RX_SDA_BIT 6
#define | RTE_I2S0_RX_SDA_FUNC 1
#define | RTE_I2S0_RX_SDA_PIN_EN 1
#define | RTE_I2S0_RX_MCLK_PIN_SEL 0
#define | RTE_I2S0_RX_MCLK_PIN_EN 0
#define | RTE_I2S0_TX_SCK_PIN_SEL 1
#define | RTE_I2S0_TX_SCK_PORT 0
#define | RTE_I2S0_TX_SCK_BIT 7
#define | RTE_I2S0_TX_SCK_FUNC 1
#define | RTE_I2S0_TX_SCK_PIN_EN 1
#define | RTE_I2S0_TX_WS_PIN_SEL 1
#define | RTE_I2S0_TX_WS_PORT 0
#define | RTE_I2S0_TX_WS_BIT 8
#define | RTE_I2S0_TX_WS_FUNC 1
#define | RTE_I2S0_TX_WS_PIN_EN 1
#define | RTE_I2S0_TX_SDA_PIN_SEL 1
#define | RTE_I2S0_TX_SDA_PORT 0
#define | RTE_I2S0_TX_SDA_BIT 9
#define | RTE_I2S0_TX_SDA_FUNC 1
#define | RTE_I2S0_TX_SDA_PIN_EN 1
#define | RTE_I2S0_TX_MCLK_PIN_SEL 1
#define | RTE_I2S0_TX_MCLK_PORT 4
#define | RTE_I2S0_TX_MCLK_BIT 29
#define | RTE_I2S0_TX_MCLK_FUNC 1
#define | RTE_I2S0_TX_MCLK_PIN_EN 1
#define | RTE_I2S0_DMA_TX_EN 1
#define | RTE_I2S0_DMA_TX_CH 0
#define | RTE_I2S0_DMA_RX_EN 1
#define | RTE_I2S0_DMA_RX_CH 1

## Macro Definition Documentation

## RTE_CAN1_RD_ID

#define RTE_CAN1_RD_ID 0

## RTE_CAN1_RD_PIN_EN

#define RTE_CAN1_RD_PIN_EN 0

## RTE_CAN1_TD_ID

#define RTE_CAN1_TD_ID 0

## RTE_CAN1_TD_PIN_EN

#define RTE_CAN1_TD_PIN_EN 0

## RTE_CAN2_RD_ID

#define RTE_CAN2_RD_ID 0

## RTE_CAN2_RD_PIN_EN

#define RTE_CAN2_RD_PIN_EN 0

## RTE_CAN2_TD_ID

#define RTE_CAN2_TD_ID 0

## RTE_CAN2_TD_PIN_EN

#define RTE_CAN2_TD_PIN_EN 0

## RTE_CAN_CAN1

#define RTE_CAN_CAN1 0

## RTE_CAN_CAN2

#define RTE_CAN_CAN2 1

## RTE_ENET

#define RTE_ENET 0

## RTE_ENET_MDI_MDC_FUNC

#define RTE_ENET_MDI_MDC_FUNC 1

## RTE_ENET_MDI_MDC_PIN

#define RTE_ENET_MDI_MDC_PIN 16

## RTE_ENET_MDI_MDC_PORT

#define RTE_ENET_MDI_MDC_PORT 1

## RTE_ENET_MDI_MDC_PORT_ID

#define RTE_ENET_MDI_MDC_PORT_ID 0

## RTE_ENET_MDI_MDIO_FUNC

#define RTE_ENET_MDI_MDIO_FUNC 1

## RTE_ENET_MDI_MDIO_PIN

#define RTE_ENET_MDI_MDIO_PIN 17

## RTE_ENET_MDI_MDIO_PORT

#define RTE_ENET_MDI_MDIO_PORT 1

## RTE_ENET_MDI_MDIO_PORT_ID

#define RTE_ENET_MDI_MDIO_PORT_ID 0

## RTE_ENET_RMII

#define RTE_ENET_RMII 1

## RTE_ENET_RMII_CRS_FUNC

#define RTE_ENET_RMII_CRS_FUNC 1

## RTE_ENET_RMII_CRS_PIN

#define RTE_ENET_RMII_CRS_PIN 8

## RTE_ENET_RMII_CRS_PORT

#define RTE_ENET_RMII_CRS_PORT 1

## RTE_ENET_RMII_CRS_PORT_ID

#define RTE_ENET_RMII_CRS_PORT_ID 0

## RTE_ENET_RMII_REF_CLK_FUNC

#define RTE_ENET_RMII_REF_CLK_FUNC 1

## RTE_ENET_RMII_REF_CLK_PIN

#define RTE_ENET_RMII_REF_CLK_PIN 15

## RTE_ENET_RMII_REF_CLK_PORT

#define RTE_ENET_RMII_REF_CLK_PORT 1

## RTE_ENET_RMII_REF_CLK_PORT_ID

#define RTE_ENET_RMII_REF_CLK_PORT_ID 0

## RTE_ENET_RMII_RX_ER_FUNC

#define RTE_ENET_RMII_RX_ER_FUNC 1

## RTE_ENET_RMII_RX_ER_PIN

#define RTE_ENET_RMII_RX_ER_PIN 14

## RTE_ENET_RMII_RX_ER_PORT

#define RTE_ENET_RMII_RX_ER_PORT 1

## RTE_ENET_RMII_RX_ER_PORT_ID

#define RTE_ENET_RMII_RX_ER_PORT_ID 0

## RTE_ENET_RMII_RXD0_FUNC

#define RTE_ENET_RMII_RXD0_FUNC 1

## RTE_ENET_RMII_RXD0_PIN

#define RTE_ENET_RMII_RXD0_PIN 9

## RTE_ENET_RMII_RXD0_PORT

#define RTE_ENET_RMII_RXD0_PORT 1

## RTE_ENET_RMII_RXD0_PORT_ID

#define RTE_ENET_RMII_RXD0_PORT_ID 0

## RTE_ENET_RMII_RXD1_FUNC

#define RTE_ENET_RMII_RXD1_FUNC 1

## RTE_ENET_RMII_RXD1_PIN

#define RTE_ENET_RMII_RXD1_PIN 10

## RTE_ENET_RMII_RXD1_PORT

#define RTE_ENET_RMII_RXD1_PORT 1

## RTE_ENET_RMII_RXD1_PORT_ID

#define RTE_ENET_RMII_RXD1_PORT_ID 0

## RTE_ENET_RMII_TX_EN_FUNC

#define RTE_ENET_RMII_TX_EN_FUNC 1

## RTE_ENET_RMII_TX_EN_PIN

#define RTE_ENET_RMII_TX_EN_PIN 4

## RTE_ENET_RMII_TX_EN_PORT

#define RTE_ENET_RMII_TX_EN_PORT 1

## RTE_ENET_RMII_TX_EN_PORT_ID

#define RTE_ENET_RMII_TX_EN_PORT_ID 0

## RTE_ENET_RMII_TXD0_FUNC

#define RTE_ENET_RMII_TXD0_FUNC 1

## RTE_ENET_RMII_TXD0_PIN

#define RTE_ENET_RMII_TXD0_PIN 0

## RTE_ENET_RMII_TXD0_PORT

#define RTE_ENET_RMII_TXD0_PORT 1

## RTE_ENET_RMII_TXD0_PORT_ID

#define RTE_ENET_RMII_TXD0_PORT_ID 0

## RTE_ENET_RMII_TXD1_FUNC

#define RTE_ENET_RMII_TXD1_FUNC 1

## RTE_ENET_RMII_TXD1_PIN

#define RTE_ENET_RMII_TXD1_PIN 1

## RTE_ENET_RMII_TXD1_PORT

#define RTE_ENET_RMII_TXD1_PORT 1

## RTE_ENET_RMII_TXD1_PORT_ID

#define RTE_ENET_RMII_TXD1_PORT_ID 0

## RTE_I2C0

#define RTE_I2C0 0

## RTE_I2C0_SCL_FUNC

#define RTE_I2C0_SCL_FUNC 1

## RTE_I2C0_SCL_PIN

#define RTE_I2C0_SCL_PIN 28

## RTE_I2C0_SCL_PORT

#define RTE_I2C0_SCL_PORT 0

## RTE_I2C0_SCL_PORT_ID

#define RTE_I2C0_SCL_PORT_ID 0

## RTE_I2C0_SDA_FUNC

#define RTE_I2C0_SDA_FUNC 1

## RTE_I2C0_SDA_PIN

#define RTE_I2C0_SDA_PIN 27

## RTE_I2C0_SDA_PORT

#define RTE_I2C0_SDA_PORT 0

## RTE_I2C0_SDA_PORT_ID

#define RTE_I2C0_SDA_PORT_ID 0

## RTE_I2C1

#define RTE_I2C1 0

## RTE_I2C1_SCL_FUNC

#define RTE_I2C1_SCL_FUNC 3

## RTE_I2C1_SCL_PIN

#define RTE_I2C1_SCL_PIN 1

## RTE_I2C1_SCL_PORT

#define RTE_I2C1_SCL_PORT 0

## RTE_I2C1_SCL_PORT_ID

#define RTE_I2C1_SCL_PORT_ID 0

## RTE_I2C1_SDA_FUNC

#define RTE_I2C1_SDA_FUNC 3

## RTE_I2C1_SDA_PIN

#define RTE_I2C1_SDA_PIN 0

## RTE_I2C1_SDA_PORT

#define RTE_I2C1_SDA_PORT 0

## RTE_I2C1_SDA_PORT_ID

#define RTE_I2C1_SDA_PORT_ID 0

## RTE_I2C2

#define RTE_I2C2 1

## RTE_I2C2_SCL_FUNC

#define RTE_I2C2_SCL_FUNC 2

## RTE_I2C2_SCL_PIN

#define RTE_I2C2_SCL_PIN 11

## RTE_I2C2_SCL_PORT

#define RTE_I2C2_SCL_PORT 0

## RTE_I2C2_SCL_PORT_ID

#define RTE_I2C2_SCL_PORT_ID 0

## RTE_I2C2_SDA_FUNC

#define RTE_I2C2_SDA_FUNC 2

## RTE_I2C2_SDA_PIN

#define RTE_I2C2_SDA_PIN 10

## RTE_I2C2_SDA_PORT

#define RTE_I2C2_SDA_PORT 0

## RTE_I2C2_SDA_PORT_ID

#define RTE_I2C2_SDA_PORT_ID 0

## RTE_I2S0

#define RTE_I2S0 0

## RTE_I2S0_DMA_RX_CH

#define RTE_I2S0_DMA_RX_CH 1

## RTE_I2S0_DMA_RX_EN

#define RTE_I2S0_DMA_RX_EN 1

## RTE_I2S0_DMA_TX_CH

#define RTE_I2S0_DMA_TX_CH 0

## RTE_I2S0_DMA_TX_EN

#define RTE_I2S0_DMA_TX_EN 1

## RTE_I2S0_RX_MCLK_PIN_EN

#define RTE_I2S0_RX_MCLK_PIN_EN 0

## RTE_I2S0_RX_MCLK_PIN_SEL

#define RTE_I2S0_RX_MCLK_PIN_SEL 0

## RTE_I2S0_RX_SCK_BIT

#define RTE_I2S0_RX_SCK_BIT 4

## RTE_I2S0_RX_SCK_FUNC

#define RTE_I2S0_RX_SCK_FUNC 1

## RTE_I2S0_RX_SCK_PIN_EN

#define RTE_I2S0_RX_SCK_PIN_EN 1

## RTE_I2S0_RX_SCK_PIN_SEL

#define RTE_I2S0_RX_SCK_PIN_SEL 1

## RTE_I2S0_RX_SCK_PORT

#define RTE_I2S0_RX_SCK_PORT 0

## RTE_I2S0_RX_SDA_BIT

#define RTE_I2S0_RX_SDA_BIT 6

## RTE_I2S0_RX_SDA_FUNC

#define RTE_I2S0_RX_SDA_FUNC 1

## RTE_I2S0_RX_SDA_PIN_EN

#define RTE_I2S0_RX_SDA_PIN_EN 1

## RTE_I2S0_RX_SDA_PIN_SEL

#define RTE_I2S0_RX_SDA_PIN_SEL 1

## RTE_I2S0_RX_SDA_PORT

#define RTE_I2S0_RX_SDA_PORT 0

## RTE_I2S0_RX_WS_BIT

#define RTE_I2S0_RX_WS_BIT 5

## RTE_I2S0_RX_WS_FUNC

#define RTE_I2S0_RX_WS_FUNC 1

## RTE_I2S0_RX_WS_PIN_EN

#define RTE_I2S0_RX_WS_PIN_EN 1

## RTE_I2S0_RX_WS_PIN_SEL

#define RTE_I2S0_RX_WS_PIN_SEL 1

## RTE_I2S0_RX_WS_PORT

#define RTE_I2S0_RX_WS_PORT 0

## RTE_I2S0_TX_MCLK_BIT

#define RTE_I2S0_TX_MCLK_BIT 29

## RTE_I2S0_TX_MCLK_FUNC

#define RTE_I2S0_TX_MCLK_FUNC 1

## RTE_I2S0_TX_MCLK_PIN_EN

#define RTE_I2S0_TX_MCLK_PIN_EN 1

## RTE_I2S0_TX_MCLK_PIN_SEL

#define RTE_I2S0_TX_MCLK_PIN_SEL 1

## RTE_I2S0_TX_MCLK_PORT

#define RTE_I2S0_TX_MCLK_PORT 4

## RTE_I2S0_TX_SCK_BIT

#define RTE_I2S0_TX_SCK_BIT 7

## RTE_I2S0_TX_SCK_FUNC

#define RTE_I2S0_TX_SCK_FUNC 1

## RTE_I2S0_TX_SCK_PIN_EN

#define RTE_I2S0_TX_SCK_PIN_EN 1

## RTE_I2S0_TX_SCK_PIN_SEL

#define RTE_I2S0_TX_SCK_PIN_SEL 1

## RTE_I2S0_TX_SCK_PORT

#define RTE_I2S0_TX_SCK_PORT 0

## RTE_I2S0_TX_SDA_BIT

#define RTE_I2S0_TX_SDA_BIT 9

## RTE_I2S0_TX_SDA_FUNC

#define RTE_I2S0_TX_SDA_FUNC 1

## RTE_I2S0_TX_SDA_PIN_EN

#define RTE_I2S0_TX_SDA_PIN_EN 1

## RTE_I2S0_TX_SDA_PIN_SEL

#define RTE_I2S0_TX_SDA_PIN_SEL 1

## RTE_I2S0_TX_SDA_PORT

#define RTE_I2S0_TX_SDA_PORT 0

## RTE_I2S0_TX_WS_BIT

#define RTE_I2S0_TX_WS_BIT 8

## RTE_I2S0_TX_WS_FUNC

#define RTE_I2S0_TX_WS_FUNC 1

## RTE_I2S0_TX_WS_PIN_EN

#define RTE_I2S0_TX_WS_PIN_EN 1

## RTE_I2S0_TX_WS_PIN_SEL

#define RTE_I2S0_TX_WS_PIN_SEL 1

## RTE_I2S0_TX_WS_PORT

#define RTE_I2S0_TX_WS_PORT 0

## RTE_SPI

#define RTE_SPI 1

## RTE_SPI_MISO_BIT

#define RTE_SPI_MISO_BIT 17

## RTE_SPI_MISO_FUNC

#define RTE_SPI_MISO_FUNC 3

## RTE_SPI_MISO_PIN_EN

#define RTE_SPI_MISO_PIN_EN 1

## RTE_SPI_MISO_PIN_SEL

#define RTE_SPI_MISO_PIN_SEL 1

## RTE_SPI_MISO_PORT

#define RTE_SPI_MISO_PORT 0

## RTE_SPI_MOSI_BIT

#define RTE_SPI_MOSI_BIT 18

## RTE_SPI_MOSI_FUNC

#define RTE_SPI_MOSI_FUNC 3

## RTE_SPI_MOSI_PIN_EN

#define RTE_SPI_MOSI_PIN_EN 1

## RTE_SPI_MOSI_PIN_SEL

#define RTE_SPI_MOSI_PIN_SEL 1

## RTE_SPI_MOSI_PORT

#define RTE_SPI_MOSI_PORT 0

## RTE_SPI_SCK_BIT

#define RTE_SPI_SCK_BIT 15

## RTE_SPI_SCK_FUNC

#define RTE_SPI_SCK_FUNC 3

## RTE_SPI_SCK_PIN_SEL

#define RTE_SPI_SCK_PIN_SEL 0

## RTE_SPI_SCK_PORT

#define RTE_SPI_SCK_PORT 0

## RTE_SPI_SSEL_BIT

#define RTE_SPI_SSEL_BIT 16

## RTE_SPI_SSEL_FUNC

#define RTE_SPI_SSEL_FUNC 3

## RTE_SPI_SSEL_PIN_EN

#define RTE_SPI_SSEL_PIN_EN 1

## RTE_SPI_SSEL_PIN_SEL

#define RTE_SPI_SSEL_PIN_SEL 1

## RTE_SPI_SSEL_PORT

#define RTE_SPI_SSEL_PORT 0

## RTE_SSP0

#define RTE_SSP0 1

## RTE_SSP0_DMA_RX_CH

#define RTE_SSP0_DMA_RX_CH 1

## RTE_SSP0_DMA_RX_EN

#define RTE_SSP0_DMA_RX_EN 0

## RTE_SSP0_DMA_TX_CH

#define RTE_SSP0_DMA_TX_CH 0

## RTE_SSP0_DMA_TX_EN

#define RTE_SSP0_DMA_TX_EN 0

## RTE_SSP0_MISO_BIT

#define RTE_SSP0_MISO_BIT 17

## RTE_SSP0_MISO_FUNC

#define RTE_SSP0_MISO_FUNC 2

## RTE_SSP0_MISO_PIN_EN

#define RTE_SSP0_MISO_PIN_EN 1

## RTE_SSP0_MISO_PIN_SEL

#define RTE_SSP0_MISO_PIN_SEL 1

## RTE_SSP0_MISO_PORT

#define RTE_SSP0_MISO_PORT 0

## RTE_SSP0_MOSI_BIT

#define RTE_SSP0_MOSI_BIT 18

## RTE_SSP0_MOSI_FUNC

#define RTE_SSP0_MOSI_FUNC 2

## RTE_SSP0_MOSI_PIN_EN

#define RTE_SSP0_MOSI_PIN_EN 1

## RTE_SSP0_MOSI_PIN_SEL

#define RTE_SSP0_MOSI_PIN_SEL 1

## RTE_SSP0_MOSI_PORT

#define RTE_SSP0_MOSI_PORT 0

## RTE_SSP0_SCK_BIT

#define RTE_SSP0_SCK_BIT 15

## RTE_SSP0_SCK_FUNC

#define RTE_SSP0_SCK_FUNC 2

## RTE_SSP0_SCK_PIN_SEL

#define RTE_SSP0_SCK_PIN_SEL 0

## RTE_SSP0_SCK_PORT

#define RTE_SSP0_SCK_PORT 0

## RTE_SSP0_SSEL_BIT

#define RTE_SSP0_SSEL_BIT 16

## RTE_SSP0_SSEL_FUNC

#define RTE_SSP0_SSEL_FUNC 2

## RTE_SSP0_SSEL_PIN_EN

#define RTE_SSP0_SSEL_PIN_EN 1

## RTE_SSP0_SSEL_PIN_SEL

#define RTE_SSP0_SSEL_PIN_SEL 1

## RTE_SSP0_SSEL_PORT

#define RTE_SSP0_SSEL_PORT 0

## RTE_SSP1

#define RTE_SSP1 1

## RTE_SSP1_DMA_RX_CH

#define RTE_SSP1_DMA_RX_CH 3

## RTE_SSP1_DMA_RX_EN

#define RTE_SSP1_DMA_RX_EN 0

## RTE_SSP1_DMA_TX_CH

#define RTE_SSP1_DMA_TX_CH 2

## RTE_SSP1_DMA_TX_EN

#define RTE_SSP1_DMA_TX_EN 0

## RTE_SSP1_MISO_BIT

#define RTE_SSP1_MISO_BIT 8

## RTE_SSP1_MISO_FUNC

#define RTE_SSP1_MISO_FUNC 2

## RTE_SSP1_MISO_PIN_EN

#define RTE_SSP1_MISO_PIN_EN 1

## RTE_SSP1_MISO_PIN_SEL

#define RTE_SSP1_MISO_PIN_SEL 1

## RTE_SSP1_MISO_PORT

#define RTE_SSP1_MISO_PORT 0

## RTE_SSP1_MOSI_BIT

#define RTE_SSP1_MOSI_BIT 9

## RTE_SSP1_MOSI_FUNC

#define RTE_SSP1_MOSI_FUNC 2

## RTE_SSP1_MOSI_PIN_EN

#define RTE_SSP1_MOSI_PIN_EN 1

## RTE_SSP1_MOSI_PIN_SEL

#define RTE_SSP1_MOSI_PIN_SEL 1

## RTE_SSP1_MOSI_PORT

#define RTE_SSP1_MOSI_PORT 0

## RTE_SSP1_SCK_BIT

#define RTE_SSP1_SCK_BIT 7

## RTE_SSP1_SCK_FUNC

#define RTE_SSP1_SCK_FUNC 2

## RTE_SSP1_SCK_PIN_SEL

#define RTE_SSP1_SCK_PIN_SEL 0

## RTE_SSP1_SCK_PORT

#define RTE_SSP1_SCK_PORT 0

## RTE_SSP1_SSEL_BIT

#define RTE_SSP1_SSEL_BIT 6

## RTE_SSP1_SSEL_FUNC

#define RTE_SSP1_SSEL_FUNC 2

## RTE_SSP1_SSEL_PIN_EN

#define RTE_SSP1_SSEL_PIN_EN 1

## RTE_SSP1_SSEL_PIN_SEL

#define RTE_SSP1_SSEL_PIN_SEL 1

## RTE_SSP1_SSEL_PORT

#define RTE_SSP1_SSEL_PORT 0

## RTE_UART0

#define RTE_UART0 0

## RTE_UART0_DMA_RX_CH

#define RTE_UART0_DMA_RX_CH 1

## RTE_UART0_DMA_RX_EN

#define RTE_UART0_DMA_RX_EN 1

## RTE_UART0_DMA_TX_CH

#define RTE_UART0_DMA_TX_CH 0

## RTE_UART0_DMA_TX_EN

#define RTE_UART0_DMA_TX_EN 1

## RTE_UART0_RX_ID

#define RTE_UART0_RX_ID 0

## RTE_UART0_RX_PIN_EN

#define RTE_UART0_RX_PIN_EN 0

## RTE_UART0_TX_ID

#define RTE_UART0_TX_ID 0

## RTE_UART0_TX_PIN_EN

#define RTE_UART0_TX_PIN_EN 0

## RTE_UART1

#define RTE_UART1 0

## RTE_UART1_CTS_ID

#define RTE_UART1_CTS_ID 0

## RTE_UART1_CTS_PIN_EN

#define RTE_UART1_CTS_PIN_EN 0

## RTE_UART1_DCD_ID

#define RTE_UART1_DCD_ID 0

## RTE_UART1_DCD_PIN_EN

#define RTE_UART1_DCD_PIN_EN 0

## RTE_UART1_DMA_RX_CH

#define RTE_UART1_DMA_RX_CH 1

## RTE_UART1_DMA_RX_EN

#define RTE_UART1_DMA_RX_EN 1

## RTE_UART1_DMA_TX_CH

#define RTE_UART1_DMA_TX_CH 0

## RTE_UART1_DMA_TX_EN

#define RTE_UART1_DMA_TX_EN 1

## RTE_UART1_DSR_ID

#define RTE_UART1_DSR_ID 0

## RTE_UART1_DSR_PIN_EN

#define RTE_UART1_DSR_PIN_EN 0

## RTE_UART1_DTR_ID

#define RTE_UART1_DTR_ID 0

## RTE_UART1_DTR_PIN_EN

#define RTE_UART1_DTR_PIN_EN 0

## RTE_UART1_RI_ID

#define RTE_UART1_RI_ID 0

## RTE_UART1_RI_PIN_EN

#define RTE_UART1_RI_PIN_EN 0

## RTE_UART1_RTS_ID

#define RTE_UART1_RTS_ID 0

## RTE_UART1_RTS_PIN_EN

#define RTE_UART1_RTS_PIN_EN 0

## RTE_UART1_RX_BIT

#define RTE_UART1_RX_BIT 16

## RTE_UART1_RX_FUNC

#define RTE_UART1_RX_FUNC 1

## RTE_UART1_RX_ID

#define RTE_UART1_RX_ID 1

## RTE_UART1_RX_PIN_EN

#define RTE_UART1_RX_PIN_EN 1

## RTE_UART1_RX_PORT

#define RTE_UART1_RX_PORT 0

## RTE_UART1_TX_BIT

#define RTE_UART1_TX_BIT 15

## RTE_UART1_TX_FUNC

#define RTE_UART1_TX_FUNC 1

## RTE_UART1_TX_ID

#define RTE_UART1_TX_ID 1

## RTE_UART1_TX_PIN_EN

#define RTE_UART1_TX_PIN_EN 1

## RTE_UART1_TX_PORT

#define RTE_UART1_TX_PORT 0

## RTE_UART2

#define RTE_UART2 0

## RTE_UART2_DMA_RX_CH

#define RTE_UART2_DMA_RX_CH 1

## RTE_UART2_DMA_RX_EN

#define RTE_UART2_DMA_RX_EN 1

## RTE_UART2_DMA_TX_CH

#define RTE_UART2_DMA_TX_CH 0

## RTE_UART2_DMA_TX_EN

#define RTE_UART2_DMA_TX_EN 1

## RTE_UART2_RX_ID

#define RTE_UART2_RX_ID 0

## RTE_UART2_RX_PIN_EN

#define RTE_UART2_RX_PIN_EN 0

## RTE_UART2_TX_ID

#define RTE_UART2_TX_ID 0

## RTE_UART2_TX_PIN_EN

#define RTE_UART2_TX_PIN_EN 0

## RTE_UART3

#define RTE_UART3 0

## RTE_UART3_DMA_RX_CH

#define RTE_UART3_DMA_RX_CH 1

## RTE_UART3_DMA_RX_EN

#define RTE_UART3_DMA_RX_EN 1

## RTE_UART3_DMA_TX_CH

#define RTE_UART3_DMA_TX_CH 0

## RTE_UART3_DMA_TX_EN

#define RTE_UART3_DMA_TX_EN 1

## RTE_UART3_RX_ID

#define RTE_UART3_RX_ID 0

## RTE_UART3_RX_PIN_EN

#define RTE_UART3_RX_PIN_EN 0

## RTE_UART3_TX_ID

#define RTE_UART3_TX_ID 0

## RTE_UART3_TX_PIN_EN

#define RTE_UART3_TX_PIN_EN 0

## RTE_USB_CONNECT_ID

#define RTE_USB_CONNECT_ID 1

## RTE_USB_CONNECT_PIN_EN

#define RTE_USB_CONNECT_PIN_EN 1

## RTE_USB_OVRCR_ID

#define RTE_USB_OVRCR_ID 0

## RTE_USB_OVRCR_PIN_EN

#define RTE_USB_OVRCR_PIN_EN 0

## RTE_USB_PPWR_ID

#define RTE_USB_PPWR_ID 1

## RTE_USB_PPWR_PIN_EN

#define RTE_USB_PPWR_PIN_EN 1

## RTE_USB_PWRD_ID

#define RTE_USB_PWRD_ID 1

## RTE_USB_PWRD_PIN_EN

#define RTE_USB_PWRD_PIN_EN 1

## RTE_USB_UP_LED_ID

#define RTE_USB_UP_LED_ID 1

## RTE_USB_UP_LED_PIN_EN

#define RTE_USB_UP_LED_PIN_EN 1

## RTE_USB_USB0

#define RTE_USB_USB0 0

## RTE_USB_VBUS_ID

#define RTE_USB_VBUS_ID 1

## RTE_USB_VBUS_PIN_EN

#define RTE_USB_VBUS_PIN_EN 1