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RTE_Device.h
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1 /* -----------------------------------------------------------------------------
2  * Copyright (c) 2013-2016 ARM Ltd.
3  *
4  * This software is provided 'as-is', without any express or implied warranty.
5  * In no event will the authors be held liable for any damages arising from
6  * the use of this software. Permission is granted to anyone to use this
7  * software for any purpose, including commercial applications, and to alter
8  * it and redistribute it freely, subject to the following restrictions:
9  *
10  * 1. The origin of this software must not be misrepresented; you must not
11  * claim that you wrote the original software. If you use this software in
12  * a product, an acknowledgment in the product documentation would be
13  * appreciated but is not required.
14  *
15  * 2. Altered source versions must be plainly marked as such, and must not be
16  * misrepresented as being the original software.
17  *
18  * 3. This notice may not be removed or altered from any source distribution.
19  *
20  * $Date: 20. April 2016
21  * $Revision: V2.4.1
22  *
23  * Project: RTE Device Configuration for NXP LPC17xx
24  * -------------------------------------------------------------------------- */
25 
26 //-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
27 
28 #ifndef __RTE_DEVICE_H
29 #define __RTE_DEVICE_H
30 
31 
32 // <e> USB Controller [Driver_USBD and Driver_USBH]
33 // <i> Configuration settings for Driver_USBD in component ::Drivers:USB Device
34 // <i> Configuration settings for Driver_USBH in component ::Drivers:USB Host
35 #define RTE_USB_USB0 0
36 
37 // <h> Pin Configuration
38 // <o> USB_PPWR (Host) <0=>Not used <1=>P1_19
39 // <i> VBUS drive signal (towards external charge pump or power management unit).
40 #define RTE_USB_PPWR_ID 1
41 #if (RTE_USB_PPWR_ID == 0)
42  #define RTE_USB_PPWR_PIN_EN 0
43 #elif (RTE_USB_PPWR_ID == 1)
44  #define RTE_USB_PPWR_PIN_EN 1
45 #else
46  #error "Invalid RTE_USB_PPWR Pin Configuration!"
47 #endif
48 
49 // <o> USB_PWRD (Host) <0=>Not used <1=>P1_22
50 // <i> Power Status for USB port.
51 #define RTE_USB_PWRD_ID 1
52 #if (RTE_USB_PWRD_ID == 0)
53  #define RTE_USB_PWRD_PIN_EN 0
54 #elif (RTE_USB_PWRD_ID == 1)
55  #define RTE_USB_PWRD_PIN_EN 1
56 #else
57  #error "Invalid RTE_USB_PWRD Pin Configuration!"
58 #endif
59 
60 // <o> USB_OVRCR (Host) <0=>Not used <1=>P1_27
61 // <i> Port power fault signal indicating overcurrent condition.
62 // <i> This signal monitors over-current on the USB bus
63 // (external circuitry required to detect over-current condition).
64 #define RTE_USB_OVRCR_ID 0
65 #if (RTE_USB_OVRCR_ID == 0)
66  #define RTE_USB_OVRCR_PIN_EN 0
67 #elif (RTE_USB_OVRCR_ID == 1)
68  #define RTE_USB_OVRCR_PIN_EN 1
69 #else
70  #error "Invalid RTE_USB_OVRCR Pin Configuration!"
71 #endif
72 
73 // <o> USB_CONNECT (Device) <0=>Not used <1=>P2_9
74 // <i> SoftConnect control signal
75 #define RTE_USB_CONNECT_ID 1
76 #if (RTE_USB_CONNECT_ID == 0)
77  #define RTE_USB_CONNECT_PIN_EN 0
78 #elif (RTE_USB_CONNECT_ID == 1)
79  #define RTE_USB_CONNECT_PIN_EN 1
80 #else
81  #error "Invalid RTE_USB_CONNECT Pin Configuration!"
82 #endif
83 
84 // <o> USB_VBUS (Device) <0=>Not used <1=>P1_30
85 // <i> VBUS status input.
86 // <i> When this function is not enabled via its corresponding PINSEL register, it is driven HIGH internally.
87 #define RTE_USB_VBUS_ID 1
88 #if (RTE_USB_VBUS_ID == 0)
89  #define RTE_USB_VBUS_PIN_EN 0
90 #elif (RTE_USB_VBUS_ID == 1)
91  #define RTE_USB_VBUS_PIN_EN 1
92 #else
93  #error "Invalid RTE_USB_VBUS Pin Configuration!"
94 #endif
95 
96 // <o> USB_UP_LED <0=>Not used <1=>P1_18
97 // <i> GoodLink LED control signal.
98 #define RTE_USB_UP_LED_ID 1
99 #if (RTE_USB_UP_LED_ID == 0)
100  #define RTE_USB_UP_LED_PIN_EN 0
101 #elif (RTE_USB_UP_LED_ID == 1)
102  #define RTE_USB_UP_LED_PIN_EN 1
103 #else
104  #error "Invalid RTE_USB_UP_LED Pin Configuration!"
105 #endif
106 
107 // </h> Pin Configuration
108 // </e> USB Controller [Driver_USBD and Driver_USBH]
109 
110 
111 // <e> ENET (Ethernet Interface) [Driver_ETH_MAC0]
112 // <i> Configuration settings for Driver_ETH_MAC0 in component ::Drivers:Ethernet MAC
113 #define RTE_ENET 0
114 
115 
116 // <h> RMII (Reduced Media Independent Interface)
117 #define RTE_ENET_RMII 1
118 
119 // <o> ENET_TXD0 Pin <0=>P1_0
120 #define RTE_ENET_RMII_TXD0_PORT_ID 0
121 #if (RTE_ENET_RMII_TXD0_PORT_ID == 0)
122 #define RTE_ENET_RMII_TXD0_PORT 1
123 #define RTE_ENET_RMII_TXD0_PIN 0
124 #define RTE_ENET_RMII_TXD0_FUNC 1
125 #else
126 #error "Invalid ENET_TXD0 Pin Configuration!"
127 #endif
128 // <o> ENET_TXD1 Pin <0=>P1_1
129 #define RTE_ENET_RMII_TXD1_PORT_ID 0
130 #if (RTE_ENET_RMII_TXD1_PORT_ID == 0)
131 #define RTE_ENET_RMII_TXD1_PORT 1
132 #define RTE_ENET_RMII_TXD1_PIN 1
133 #define RTE_ENET_RMII_TXD1_FUNC 1
134 #else
135 #error "Invalid ENET_TXD1 Pin Configuration!"
136 #endif
137 // <o> ENET_REF_CLK Pin <0=>P1_15
138 #define RTE_ENET_RMII_REF_CLK_PORT_ID 0
139 #if (RTE_ENET_RMII_REF_CLK_PORT_ID == 0)
140 #define RTE_ENET_RMII_REF_CLK_PORT 1
141 #define RTE_ENET_RMII_REF_CLK_PIN 15
142 #define RTE_ENET_RMII_REF_CLK_FUNC 1
143 #else
144 #error "Invalid ENET_REF_CLK Pin Configuration!"
145 #endif
146 // <o> ENET_TX_EN Pin <0=>P1_4
147 #define RTE_ENET_RMII_TX_EN_PORT_ID 0
148 #if (RTE_ENET_RMII_TX_EN_PORT_ID == 0)
149 #define RTE_ENET_RMII_TX_EN_PORT 1
150 #define RTE_ENET_RMII_TX_EN_PIN 4
151 #define RTE_ENET_RMII_TX_EN_FUNC 1
152 #else
153 #error "Invalid ENET_TX_EN Pin Configuration!"
154 #endif
155 // <o> ENET_CRS Pin <0=>P1_8
156 #define RTE_ENET_RMII_CRS_PORT_ID 0
157 #if (RTE_ENET_RMII_CRS_PORT_ID == 0)
158 #define RTE_ENET_RMII_CRS_PORT 1
159 #define RTE_ENET_RMII_CRS_PIN 8
160 #define RTE_ENET_RMII_CRS_FUNC 1
161 #else
162 #error "Invalid ENET_CRS Pin Configuration!"
163 #endif
164 // <o> ENET_RXD0 Pin <0=>P1_9
165 #define RTE_ENET_RMII_RXD0_PORT_ID 0
166 #if (RTE_ENET_RMII_RXD0_PORT_ID == 0)
167 #define RTE_ENET_RMII_RXD0_PORT 1
168 #define RTE_ENET_RMII_RXD0_PIN 9
169 #define RTE_ENET_RMII_RXD0_FUNC 1
170 #else
171 #error "Invalid ENET_RXD0 Pin Configuration!"
172 #endif
173 // <o> ENET_RXD1 Pin <0=>P1_10
174 #define RTE_ENET_RMII_RXD1_PORT_ID 0
175 #if (RTE_ENET_RMII_RXD1_PORT_ID == 0)
176 #define RTE_ENET_RMII_RXD1_PORT 1
177 #define RTE_ENET_RMII_RXD1_PIN 10
178 #define RTE_ENET_RMII_RXD1_FUNC 1
179 #else
180 #error "Invalid ENET_RXD1 Pin Configuration!"
181 #endif
182 // <o> ENET_RX_ER Pin <0=>P1_14
183 #define RTE_ENET_RMII_RX_ER_PORT_ID 0
184 #if (RTE_ENET_RMII_RX_ER_PORT_ID == 0)
185 #define RTE_ENET_RMII_RX_ER_PORT 1
186 #define RTE_ENET_RMII_RX_ER_PIN 14
187 #define RTE_ENET_RMII_RX_ER_FUNC 1
188 #else
189 #error "Invalid ENET_REF_CLK Pin Configuration!"
190 #endif
191 // </h>
192 
193 // <h> MIIM (Management Data Interface)
194 // <o> ENET_MDC Pin <0=>P1_16 <1=>P2_8
195 #define RTE_ENET_MDI_MDC_PORT_ID 0
196 #if (RTE_ENET_MDI_MDC_PORT_ID == 0)
197 #define RTE_ENET_MDI_MDC_PORT 1
198 #define RTE_ENET_MDI_MDC_PIN 16
199 #define RTE_ENET_MDI_MDC_FUNC 1
200 #elif (RTE_ENET_MDI_MDC_PORT_ID == 1)
201 #define RTE_ENET_MDI_MDC_PORT 2
202 #define RTE_ENET_MDI_MDC_PIN 8
203 #define RTE_ENET_MDI_MDC_FUNC 3
204 #else
205 #error "Invalid ENET_MDC Pin Configuration!"
206 #endif
207 // <o> ENET_MDIO Pin <0=>P1_17 <1=>P2_9
208 #define RTE_ENET_MDI_MDIO_PORT_ID 0
209 #if (RTE_ENET_MDI_MDIO_PORT_ID == 0)
210 #define RTE_ENET_MDI_MDIO_PORT 1
211 #define RTE_ENET_MDI_MDIO_PIN 17
212 #define RTE_ENET_MDI_MDIO_FUNC 1
213 #elif (RTE_ENET_MDI_MDIO_PORT_ID == 1)
214 #define RTE_ENET_MDI_MDIO_PORT 2
215 #define RTE_ENET_MDI_MDIO_PIN 9
216 #define RTE_ENET_MDI_MDIO_FUNC 3
217 #else
218 #error "Invalid ENET_MDIO Pin Configuration!"
219 #endif
220 // </h>
221 
222 // </e>
223 
224 
225 // <e> I2C0 (Inter-integrated Circuit Interface 0) [Driver_I2C0]
226 // <i> Configuration settings for Driver_I2C0 in component ::Drivers:I2C
227 #define RTE_I2C0 0
228 
229 // <o> I2C0_SCL Pin <0=>P0_28
230 #define RTE_I2C0_SCL_PORT_ID 0
231 #if (RTE_I2C0_SCL_PORT_ID == 0)
232 #define RTE_I2C0_SCL_PORT 0
233 #define RTE_I2C0_SCL_PIN 28
234 #define RTE_I2C0_SCL_FUNC 1
235 #else
236 #error "Invalid I2C0_SCL Pin Configuration!"
237 #endif
238 
239 // <o> I2C0_SDA Pin <0=>P0_27
240 #define RTE_I2C0_SDA_PORT_ID 0
241 #if (RTE_I2C0_SDA_PORT_ID == 0)
242 #define RTE_I2C0_SDA_PORT 0
243 #define RTE_I2C0_SDA_PIN 27
244 #define RTE_I2C0_SDA_FUNC 1
245 #else
246 #error "Invalid I2C0_SDA Pin Configuration!"
247 #endif
248 
249 // </e>
250 
251 
252 // <e> I2C1 (Inter-integrated Circuit Interface 1) [Driver_I2C1]
253 // <i> Configuration settings for Driver_I2C1 in component ::Drivers:I2C
254 #define RTE_I2C1 0
255 
256 // <o> I2C1_SCL Pin <0=>P0_1 <1=>P0_20
257 #define RTE_I2C1_SCL_PORT_ID 0
258 #if (RTE_I2C1_SCL_PORT_ID == 0)
259 #define RTE_I2C1_SCL_PORT 0
260 #define RTE_I2C1_SCL_PIN 1
261 #define RTE_I2C1_SCL_FUNC 3
262 #elif (RTE_I2C1_SCL_PORT_ID == 1)
263 #define RTE_I2C1_SCL_PORT 0
264 #define RTE_I2C1_SCL_PIN 20
265 #define RTE_I2C1_SCL_FUNC 3
266 #else
267 #error "Invalid I2C1_SCL Pin Configuration!"
268 #endif
269 
270 // <o> I2C1_SDA Pin <0=>P0_0 <1=>P0_19
271 #define RTE_I2C1_SDA_PORT_ID 0
272 #if (RTE_I2C1_SDA_PORT_ID == 0)
273 #define RTE_I2C1_SDA_PORT 0
274 #define RTE_I2C1_SDA_PIN 0
275 #define RTE_I2C1_SDA_FUNC 3
276 #elif (RTE_I2C1_SDA_PORT_ID == 1)
277 #define RTE_I2C1_SDA_PORT 0
278 #define RTE_I2C1_SDA_PIN 19
279 #define RTE_I2C1_SDA_FUNC 3
280 #else
281 #error "Invalid I2C1_SDA Pin Configuration!"
282 #endif
283 
284 // </e>
285 
286 
287 // <e> I2C2 (Inter-integrated Circuit Interface 2) [Driver_I2C2]
288 // <i> Configuration settings for Driver_I2C2 in component ::Drivers:I2C
289 #define RTE_I2C2 1
290 
291 // <o> I2C2_SCL Pin <0=>P0_11
292 #define RTE_I2C2_SCL_PORT_ID 0
293 #if (RTE_I2C2_SCL_PORT_ID == 0)
294 #define RTE_I2C2_SCL_PORT 0
295 #define RTE_I2C2_SCL_PIN 11
296 #define RTE_I2C2_SCL_FUNC 2
297 #else
298 #error "Invalid I2C2_SCL Pin Configuration!"
299 #endif
300 
301 // <o> I2C2_SDA Pin <0=>P0_10
302 #define RTE_I2C2_SDA_PORT_ID 0
303 #if (RTE_I2C2_SDA_PORT_ID == 0)
304 #define RTE_I2C2_SDA_PORT 0
305 #define RTE_I2C2_SDA_PIN 10
306 #define RTE_I2C2_SDA_FUNC 2
307 #else
308 #error "Invalid I2C2_SDA Pin Configuration!"
309 #endif
310 
311 // </e>
312 
313 // <e> UART0 (Universal asynchronous receiver transmitter)
314 #define RTE_UART0 0
315 
316 // <o> UART0_TX Pin <0=>Not used <1=>P0_2
317 // <i> UART0 Serial Output pin
318 #define RTE_UART0_TX_ID 0
319 #if (RTE_UART0_TX_ID == 0)
320 #define RTE_UART0_TX_PIN_EN 0
321 #elif (RTE_UART0_TX_ID == 1)
322 #define RTE_UART0_TX_PORT 0
323 #define RTE_UART0_TX_BIT 2
324 #define RTE_UART0_TX_FUNC 1
325 #else
326 #error "Invalid UART0_TX Pin Configuration!"
327 #endif
328 #ifndef RTE_UART0_TX_PIN_EN
329 #define RTE_UART0_TX_PIN_EN 1
330 #endif
331 
332 // <o> UART0_RX Pin <0=>Not used <1=>P0_3
333 // <i> UART0 Serial Input pin
334 #define RTE_UART0_RX_ID 0
335 #if (RTE_UART0_RX_ID == 0)
336 #define RTE_UART0_RX_PIN_EN 0
337 #elif (RTE_UART0_RX_ID == 1)
338 #define RTE_UART0_RX_PORT 0
339 #define RTE_UART0_RX_BIT 3
340 #define RTE_UART0_RX_FUNC 1
341 #else
342 #error "Invalid UART0_RX Pin Configuration!"
343 #endif
344 #ifndef RTE_UART0_RX_PIN_EN
345 #define RTE_UART0_RX_PIN_EN 1
346 #endif
347 
348 // <h> DMA
349 // <e> Tx
350 // <o1> Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
351 // </e>
352 #define RTE_UART0_DMA_TX_EN 1
353 #define RTE_UART0_DMA_TX_CH 0
354 // <e> Rx
355 // <o1> Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
356 // </e>
357 #define RTE_UART0_DMA_RX_EN 1
358 #define RTE_UART0_DMA_RX_CH 1
359 // </h> DMA
360 
361 // </e>
362 // <e> UART1 (Universal asynchronous receiver transmitter)
363 #define RTE_UART1 0
364 
365 // <o> U1_TX Pin <0=>Not used <1=>P0_15 <2=>P2_0
366 // <i> UART1 Serial Output pin
367 #define RTE_UART1_TX_ID 1
368 #if (RTE_UART1_TX_ID == 0)
369 #define RTE_UART1_TX_PIN_EN 0
370 #elif (RTE_UART1_TX_ID == 1)
371 #define RTE_UART1_TX_PORT 0
372 #define RTE_UART1_TX_BIT 15
373 #define RTE_UART1_TX_FUNC 1
374 #elif (RTE_UART1_TX_ID == 2)
375 #define RTE_UART1_TX_PORT 2
376 #define RTE_UART1_TX_BIT 0
377 #define RTE_UART1_TX_FUNC 2
378 #else
379 #error "Invalid U1_TX Pin Configuration!"
380 #endif
381 #ifndef RTE_UART1_TX_PIN_EN
382 #define RTE_UART1_TX_PIN_EN 1
383 #endif
384 
385 // <o> U1_RX Pin <0=>Not used <1=>P0_16 <2=>P2_1
386 // <i> UART1 Serial Input pin
387 #define RTE_UART1_RX_ID 1
388 #if (RTE_UART1_RX_ID == 0)
389 #define RTE_UART1_RX_PIN_EN 0
390 #elif (RTE_UART1_RX_ID == 1)
391 #define RTE_UART1_RX_PORT 0
392 #define RTE_UART1_RX_BIT 16
393 #define RTE_UART1_RX_FUNC 1
394 #elif (RTE_UART1_RX_ID == 2)
395 #define RTE_UART1_RX_PORT 2
396 #define RTE_UART1_RX_BIT 1
397 #define RTE_UART1_RX_FUNC 2
398 #else
399 #error "Invalid U1_RX Pin Configuration!"
400 #endif
401 #ifndef RTE_UART1_RX_PIN_EN
402 #define RTE_UART1_RX_PIN_EN 1
403 #endif
404 
405 // <h> Modem Lines
406 // <o> CTS <0=>Not used <1=>P0_17 <2=>P2_2
407 #define RTE_UART1_CTS_ID 0
408 #if (RTE_UART1_CTS_ID == 0)
409 #define RTE_UART1_CTS_PIN_EN 0
410 #elif (RTE_UART1_CTS_ID == 1)
411 #define RTE_UART1_CTS_PORT 0
412 #define RTE_UART1_CTS_BIT 17
413 #define RTE_UART1_CTS_FUNC 1
414 #elif (RTE_UART1_CTS_ID == 2)
415 #define RTE_UART1_CTS_PORT 2
416 #define RTE_UART1_CTS_BIT 2
417 #define RTE_UART1_CTS_FUNC 2
418 #else
419 #error "Invalid U1_CTS Pin Configuration!"
420 #endif
421 #ifndef RTE_UART1_CTS_PIN_EN
422 #define RTE_UART1_CTS_PIN_EN 1
423 #endif
424 
425 //
426 // <o> DCD <0=>Not used <1=>P0_18 <2=>P2_3
427 #define RTE_UART1_DCD_ID 0
428 #if (RTE_UART1_DCD_ID == 0)
429 #define RTE_UART1_DCD_PIN_EN 0
430 #elif (RTE_UART1_DCD_ID == 1)
431 #define RTE_UART1_DCD_PORT 0
432 #define RTE_UART1_DCD_BIT 18
433 #define RTE_UART1_DCD_FUNC 1
434 #elif (RTE_UART1_DCD_ID == 2)
435 #define RTE_UART1_DCD_PORT 2
436 #define RTE_UART1_DCD_BIT 3
437 #define RTE_UART1_DCD_FUNC 2
438 #else
439 #error "Invalid UART1_DCD Pin Configuration!"
440 #endif
441 #ifndef RTE_UART1_DCD_PIN_EN
442 #define RTE_UART1_DCD_PIN_EN 1
443 #endif
444 
445 // <o> DSR <0=>Not used <1=>P0_19 <2=>P2_4
446 #define RTE_UART1_DSR_ID 0
447 #if (RTE_UART1_DSR_ID == 0)
448 #define RTE_UART1_DSR_PIN_EN 0
449 #elif (RTE_UART1_DSR_ID == 1)
450 #define RTE_UART1_DSR_PORT 0
451 #define RTE_UART1_DSR_BIT 19
452 #define RTE_UART1_DSR_FUNC 1
453 #elif (RTE_UART1_DSR_ID == 2)
454 #define RTE_UART1_DSR_PORT 2
455 #define RTE_UART1_DSR_BIT 4
456 #define RTE_UART1_DSR_FUNC 2
457 #else
458 #error "Invalid UART1_DSR Pin Configuration!"
459 #endif
460 #ifndef RTE_UART1_DSR_PIN_EN
461 #define RTE_UART1_DSR_PIN_EN 1
462 #endif
463 
464 // <o> DTR <0=>Not used <1=>P0_20 <2=>P2_5
465 #define RTE_UART1_DTR_ID 0
466 #if (RTE_UART1_DTR_ID == 0)
467 #define RTE_UART1_DTR_PIN_EN 0
468 #elif (RTE_UART1_DTR_ID == 1)
469 #define RTE_UART1_DTR_PORT 0
470 #define RTE_UART1_DTR_BIT 20
471 #define RTE_UART1_DTR_FUNC 1
472 #elif (RTE_UART1_DTR_ID == 2)
473 #define RTE_UART1_DTR_PORT 2
474 #define RTE_UART1_DTR_BIT 5
475 #define RTE_UART1_DTR_FUNC 2
476 #else
477 #error "Invalid UART1_DTR Pin Configuration!"
478 #endif
479 #ifndef RTE_UART1_DTR_PIN_EN
480 #define RTE_UART1_DTR_PIN_EN 1
481 #endif
482 
483 // <o> RI <0=>Not used <1=>P0_21 <2=>P2_6
484 #define RTE_UART1_RI_ID 0
485 #if (RTE_UART1_RI_ID == 0)
486 #define RTE_UART1_RI_PIN_EN 0
487 #elif (RTE_UART1_RI_ID == 1)
488 #define RTE_UART1_RI_PORT 0
489 #define RTE_UART1_RI_BIT 21
490 #define RTE_UART1_RI_FUNC 1
491 #elif (RTE_UART1_RI_ID == 2)
492 #define RTE_UART1_RI_PORT 2
493 #define RTE_UART1_RI_BIT 6
494 #define RTE_UART1_RI_FUNC 2
495 #else
496 #error "Invalid UART1_RI Pin Configuration!"
497 #endif
498 #ifndef RTE_UART1_RI_PIN_EN
499 #define RTE_UART1_RI_PIN_EN 1
500 #endif
501 
502 // <o> RTS <0=>Not used <1=>P0_22 <2=>P2_7
503 #define RTE_UART1_RTS_ID 0
504 #if (RTE_UART1_RTS_ID == 0)
505 #define RTE_UART1_RTS_PIN_EN 0
506 #elif (RTE_UART1_RTS_ID == 1)
507 #define RTE_UART1_RTS_PORT 0
508 #define RTE_UART1_RTS_BIT 22
509 #define RTE_UART1_RTS_FUNC 1
510 #elif (RTE_UART1_RTS_ID == 2)
511 #define RTE_UART1_RTS_PORT 2
512 #define RTE_UART1_RTS_BIT 7
513 #define RTE_UART1_RTS_FUNC 2
514 #else
515 #error "Invalid UART1_RTS Pin Configuration!"
516 #endif
517 #ifndef RTE_UART1_RTS_PIN_EN
518 #define RTE_UART1_RTS_PIN_EN 1
519 #endif
520 
521 // </h>
522 
523 // <h> DMA
524 // <e> Tx
525 // <o1> Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
526 // </e>
527 #define RTE_UART1_DMA_TX_EN 1
528 #define RTE_UART1_DMA_TX_CH 0
529 // <e> Rx
530 // <o1> Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
531 // </e>
532 #define RTE_UART1_DMA_RX_EN 1
533 #define RTE_UART1_DMA_RX_CH 1
534 // </h> DMA
535 
536 // </e>
537 
538 // <e> UART2 (Universal asynchronous receiver transmitter)
539 #define RTE_UART2 0
540 
541 // <o> UART2_TX Pin <0=>Not used <1=>P0_10 <2=>P2_8
542 // <i> UART2 Serial Output pin
543 #define RTE_UART2_TX_ID 0
544 #if (RTE_UART2_TX_ID == 0)
545 #define RTE_UART2_TX_PIN_EN 0
546 #elif (RTE_UART2_TX_ID == 1)
547 #define RTE_UART2_TX_PORT 0
548 #define RTE_UART2_TX_BIT 10
549 #define RTE_UART2_TX_FUNC 1
550 #elif (RTE_UART2_TX_ID == 2)
551 #define RTE_UART2_TX_PORT 2
552 #define RTE_UART2_TX_BIT 8
553 #define RTE_UART2_TX_FUNC 2
554 #else
555 #error "Invalid UART2_TX Pin Configuration!"
556 #endif
557 #ifndef RTE_UART2_TX_PIN_EN
558 #define RTE_UART2_TX_PIN_EN 1
559 #endif
560 
561 // <o> UART2_RX Pin <0=>Not used <1=>P0_11 <2=>P2_9
562 // <i> UART2 Serial Input pin
563 #define RTE_UART2_RX_ID 0
564 #if (RTE_UART2_RX_ID == 0)
565 #define RTE_UART2_RX_PIN_EN 0
566 #elif (RTE_UART2_RX_ID == 1)
567 #define RTE_UART2_RX_PORT 0
568 #define RTE_UART2_RX_BIT 11
569 #define RTE_UART2_RX_FUNC 1
570 #elif (RTE_UART2_RX_ID == 2)
571 #define RTE_UART2_RX_PORT 2
572 #define RTE_UART2_RX_BIT 9
573 #define RTE_UART2_RX_FUNC 2
574 #else
575 #error "Invalid UART2_RX Pin Configuration!"
576 #endif
577 #ifndef RTE_UART2_RX_PIN_EN
578 #define RTE_UART2_RX_PIN_EN 1
579 #endif
580 
581 // <h> DMA
582 // <e> Tx
583 // <o1> Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
584 // </e>
585 #define RTE_UART2_DMA_TX_EN 1
586 #define RTE_UART2_DMA_TX_CH 0
587 // <e> Rx
588 // <o1> Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
589 // </e>
590 #define RTE_UART2_DMA_RX_EN 1
591 #define RTE_UART2_DMA_RX_CH 1
592 // </h> DMA
593 
594 // </e>
595 
596 // <e> UART3 (Universal asynchronous receiver transmitter)
597 #define RTE_UART3 0
598 
599 // <o> UART3_TX Pin <0=>Not used <1=>P0_0 <2=>P0_25 <3=>P4_28
600 // <i> UART3 Serial Output pin
601 #define RTE_UART3_TX_ID 0
602 #if (RTE_UART3_TX_ID == 0)
603 #define RTE_UART3_TX_PIN_EN 0
604 #elif (RTE_UART3_TX_ID == 1)
605 #define RTE_UART3_TX_PORT 0
606 #define RTE_UART3_TX_BIT 0
607 #define RTE_UART3_TX_FUNC 2
608 #elif (RTE_UART3_TX_ID == 2)
609 #define RTE_UART3_TX_PORT 0
610 #define RTE_UART3_TX_BIT 25
611 #define RTE_UART3_TX_FUNC 3
612 #elif (RTE_UART3_TX_ID == 3)
613 #define RTE_UART3_TX_PORT 4
614 #define RTE_UART3_TX_BIT 28
615 #define RTE_UART3_TX_FUNC 3
616 #else
617 #error "Invalid UART3_TX Pin Configuration!"
618 #endif
619 #ifndef RTE_UART3_TX_PIN_EN
620 #define RTE_UART3_TX_PIN_EN 1
621 #endif
622 
623 // <o> UART3_RX Pin <0=>Not used <1=>P0_1 <2=>P0_26 <3=>P4_29
624 // <i> UART3 Serial Input pin
625 #define RTE_UART3_RX_ID 0
626 #if (RTE_UART3_RX_ID == 0)
627 #define RTE_UART3_RX_PIN_EN 0
628 #elif (RTE_UART3_RX_ID == 1)
629 #define RTE_UART3_RX_PORT 0
630 #define RTE_UART3_RX_BIT 1
631 #define RTE_UART3_RX_FUNC 2
632 #elif (RTE_UART3_RX_ID == 2)
633 #define RTE_UART3_RX_PORT 0
634 #define RTE_UART3_RX_BIT 26
635 #define RTE_UART3_RX_FUNC 3
636 #elif (RTE_UART3_RX_ID == 3)
637 #define RTE_UART3_RX_PORT 4
638 #define RTE_UART3_RX_BIT 29
639 #define RTE_UART3_RX_FUNC 3
640 #else
641 #error "Invalid UART3_RX Pin Configuration!"
642 #endif
643 #ifndef RTE_UART3_RX_PIN_EN
644 #define RTE_UART3_RX_PIN_EN 1
645 #endif
646 
647 // <h> DMA
648 // <e> Tx
649 // <o1> Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
650 // </e>
651 #define RTE_UART3_DMA_TX_EN 1
652 #define RTE_UART3_DMA_TX_CH 0
653 // <e> Rx
654 // <o1> Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
655 // </e>
656 #define RTE_UART3_DMA_RX_EN 1
657 #define RTE_UART3_DMA_RX_CH 1
658 // </h> DMA
659 
660 // </e>
661 
662 // <e> CAN1 Controller [Driver_CAN1]
663 // <i> Configuration settings for Driver_CAN1 in component ::Drivers:CAN
664 #define RTE_CAN_CAN1 0
665 
666 // <h> Pin Configuration
667 // <o> CAN1_RD <0=>Not used <1=>P0_0 <2=>P0_21
668 // <i> CAN1 receiver input.
669 #define RTE_CAN1_RD_ID 0
670 #if (RTE_CAN1_RD_ID == 0)
671  #define RTE_CAN1_RD_PIN_EN 0
672 #elif (RTE_CAN1_RD_ID == 1)
673  #define RTE_CAN1_RD_PORT 0
674  #define RTE_CAN1_RD_BIT 0
675  #define RTE_CAN1_RD_FUNC 1
676 #elif (RTE_CAN1_RD_ID == 2)
677  #define RTE_CAN1_RD_PORT 0
678  #define RTE_CAN1_RD_BIT 21
679  #define RTE_CAN1_RD_FUNC 3
680 #else
681  #error "Invalid RTE_CAN1_RD Pin Configuration!"
682 #endif
683 #ifndef RTE_CAN1_RD_PIN_EN
684  #define RTE_CAN1_RD_PIN_EN 1
685 #endif
686 // <o> CAN1_TD <0=>Not used <1=>P0_1 <2=>P0_22
687 // <i> CAN1 transmitter output.
688 #define RTE_CAN1_TD_ID 0
689 #if (RTE_CAN1_TD_ID == 0)
690  #define RTE_CAN1_TD_PIN_EN 0
691 #elif (RTE_CAN1_TD_ID == 1)
692  #define RTE_CAN1_TD_PORT 0
693  #define RTE_CAN1_TD_BIT 1
694  #define RTE_CAN1_TD_FUNC 1
695 #elif (RTE_CAN1_TD_ID == 2)
696  #define RTE_CAN1_TD_PORT 0
697  #define RTE_CAN1_TD_BIT 22
698  #define RTE_CAN1_TD_FUNC 3
699 #else
700  #error "Invalid RTE_CAN1_TD Pin Configuration!"
701 #endif
702 #ifndef RTE_CAN1_TD_PIN_EN
703  #define RTE_CAN1_TD_PIN_EN 1
704 #endif
705 // </h> Pin Configuration
706 // </e> CAN1 Controller [Driver_CAN1]
707 
708 // <e> CAN2 Controller [Driver_CAN2]
709 // <i> Configuration settings for Driver_CAN2 in component ::Drivers:CAN
710 #define RTE_CAN_CAN2 1
711 
712 // <h> Pin Configuration
713 // <o> CAN2_RD <0=>Not used <1=>P0_4 <2=>P2_7
714 // <i> CAN2 receiver input.
715 #define RTE_CAN2_RD_ID 0
716 #if (RTE_CAN2_RD_ID == 0)
717  #define RTE_CAN2_RD_PIN_EN 0
718 #elif (RTE_CAN2_RD_ID == 1)
719  #define RTE_CAN2_RD_PORT 0
720  #define RTE_CAN2_RD_BIT 4
721  #define RTE_CAN2_RD_FUNC 2
722 #elif (RTE_CAN2_RD_ID == 2)
723  #define RTE_CAN2_RD_PORT 2
724  #define RTE_CAN2_RD_BIT 7
725  #define RTE_CAN2_RD_FUNC 1
726 #else
727  #error "Invalid RTE_CAN2_RD Pin Configuration!"
728 #endif
729 #ifndef RTE_CAN2_RD_PIN_EN
730  #define RTE_CAN2_RD_PIN_EN 1
731 #endif
732 // <o> CAN2_TD <0=>Not used <1=>P0_5 <2=>P2_8
733 // <i> CAN2 transmitter output.
734 #define RTE_CAN2_TD_ID 0
735 #if (RTE_CAN2_TD_ID == 0)
736  #define RTE_CAN2_TD_PIN_EN 0
737 #elif (RTE_CAN2_TD_ID == 1)
738  #define RTE_CAN2_TD_PORT 0
739  #define RTE_CAN2_TD_BIT 5
740  #define RTE_CAN2_TD_FUNC 2
741 #elif (RTE_CAN2_TD_ID == 2)
742  #define RTE_CAN2_TD_PORT 2
743  #define RTE_CAN2_TD_BIT 8
744  #define RTE_CAN2_TD_FUNC 1
745 #else
746  #error "Invalid RTE_CAN2_TD Pin Configuration!"
747 #endif
748 #ifndef RTE_CAN2_TD_PIN_EN
749  #define RTE_CAN2_TD_PIN_EN 1
750 #endif
751 // </h> Pin Configuration
752 // </e> CAN2 Controller [Driver_CAN2]
753 
754 
755 // <e> SSP0 (Synchronous Serial Port 0) [Driver_SPI0]
756 // <i> Configuration settings for Driver_SPI0 in component ::Drivers:SPI
757 #define RTE_SSP0 1
758 
759 // <h> Pin Configuration
760 // <o> SSP0_SSEL <0=>Not used <1=>P0_16 <2=>P1_21
761 // <i> Slave Select for SSP0
762 #define RTE_SSP0_SSEL_PIN_SEL 1
763 #if (RTE_SSP0_SSEL_PIN_SEL == 0)
764 #define RTE_SSP0_SSEL_PIN_EN 0
765 #elif (RTE_SSP0_SSEL_PIN_SEL == 1)
766  #define RTE_SSP0_SSEL_PORT 0
767  #define RTE_SSP0_SSEL_BIT 16
768  #define RTE_SSP0_SSEL_FUNC 2
769 #elif (RTE_SSP0_SSEL_PIN_SEL == 2)
770  #define RTE_SSP0_SSEL_PORT 1
771  #define RTE_SSP0_SSEL_BIT 21
772  #define RTE_SSP0_SSEL_FUNC 3
773 #else
774  #error "Invalid SSP0 SSP0_SSEL Pin Configuration!"
775 #endif
776 #ifndef RTE_SSP0_SSEL_PIN_EN
777 #define RTE_SSP0_SSEL_PIN_EN 1
778 #endif
779 
780 // <o> SSP0_SCK <0=>P0_15 <1=>P1_20
781 // <i> Serial clock for SSP0
782 #define RTE_SSP0_SCK_PIN_SEL 0
783 #if (RTE_SSP0_SCK_PIN_SEL == 0)
784  #define RTE_SSP0_SCK_PORT 0
785  #define RTE_SSP0_SCK_BIT 15
786  #define RTE_SSP0_SCK_FUNC 2
787 #elif (RTE_SSP0_SCK_PIN_SEL == 1)
788  #define RTE_SSP0_SCK_PORT 1
789  #define RTE_SSP0_SCK_BIT 20
790  #define RTE_SSP0_SCK_FUNC 3
791 #else
792  #error "Invalid SSP0 SSP0_SCK Pin Configuration!"
793 #endif
794 
795 // <o> SSP0_MISO <0=>Not used <1=>P0_17 <2=>P1_23
796 // <i> Master In Slave Out for SSP0
797 #define RTE_SSP0_MISO_PIN_SEL 1
798 #if (RTE_SSP0_MISO_PIN_SEL == 0)
799  #define RTE_SSP0_MISO_PIN_EN 0
800 #elif (RTE_SSP0_MISO_PIN_SEL == 1)
801  #define RTE_SSP0_MISO_PORT 0
802  #define RTE_SSP0_MISO_BIT 17
803  #define RTE_SSP0_MISO_FUNC 2
804 #elif (RTE_SSP0_MISO_PIN_SEL == 2)
805  #define RTE_SSP0_MISO_PORT 1
806  #define RTE_SSP0_MISO_BIT 23
807  #define RTE_SSP0_MISO_FUNC 3
808 #else
809  #error "Invalid SSP0 SSP0_MISO Pin Configuration!"
810 #endif
811 #ifndef RTE_SSP0_MISO_PIN_EN
812 #define RTE_SSP0_MISO_PIN_EN 1
813 #endif
814 
815 // <o> SSP0_MOSI <0=>Not used <1=>P0_18 <2=>P1_24
816 // <i> Master Out Slave In for SSP0
817 #define RTE_SSP0_MOSI_PIN_SEL 1
818 #if (RTE_SSP0_MOSI_PIN_SEL == 0)
819  #define RTE_SSP0_MOSI_PIN_EN 0
820 #elif (RTE_SSP0_MOSI_PIN_SEL == 1)
821  #define RTE_SSP0_MOSI_PORT 0
822  #define RTE_SSP0_MOSI_BIT 18
823  #define RTE_SSP0_MOSI_FUNC 2
824 #elif (RTE_SSP0_MOSI_PIN_SEL == 2)
825  #define RTE_SSP0_MOSI_PORT 1
826  #define RTE_SSP0_MOSI_BIT 24
827  #define RTE_SSP0_MOSI_FUNC 3
828 #else
829  #error "Invalid SSP0 SSP0_MOSI Pin Configuration!"
830 #endif
831 #ifndef RTE_SSP0_MOSI_PIN_EN
832 #define RTE_SSP0_MOSI_PIN_EN 1
833 #endif
834 
835 // </h>
836 // <h> DMA
837 // <e> Tx
838 // <o1> Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
839 // </e>
840 #define RTE_SSP0_DMA_TX_EN 0
841 #define RTE_SSP0_DMA_TX_CH 0
842 // <e> Rx
843 // <o1> Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
844 // </e>
845 #define RTE_SSP0_DMA_RX_EN 0
846 #define RTE_SSP0_DMA_RX_CH 1
847 // </h> DMA
848 // </e>
849 
850 // <e> SSP1 (Synchronous Serial Port 1) [Driver_SPI1]
851 // <i> Configuration settings for Driver_SPI1 in component ::Drivers:SPI
852 #define RTE_SSP1 1
853 
854 // <h> Pin Configuration
855 // <o> SSP1_SSEL <0=>Not used <1=>P0_6
856 // <i> Slave Select for SSP1
857 #define RTE_SSP1_SSEL_PIN_SEL 1
858 #if (RTE_SSP1_SSEL_PIN_SEL == 0)
859  #define RTE_SSP1_SSEL_PIN_EN 0
860 #elif (RTE_SSP1_SSEL_PIN_SEL == 1)
861  #define RTE_SSP1_SSEL_PORT 0
862  #define RTE_SSP1_SSEL_BIT 6
863  #define RTE_SSP1_SSEL_FUNC 2
864 #else
865  #error "Invalid SSP1 SSP1_SSEL Pin Configuration!"
866 #endif
867 #ifndef RTE_SSP1_SSEL_PIN_EN
868 #define RTE_SSP1_SSEL_PIN_EN 1
869 #endif
870 
871 // <o> SSP1_SCK <0=>P0_7 <1=>P1_31
872 // <i> Serial clock for SSP1
873 #define RTE_SSP1_SCK_PIN_SEL 0
874 #if (RTE_SSP1_SCK_PIN_SEL == 0)
875  #define RTE_SSP1_SCK_PORT 0
876  #define RTE_SSP1_SCK_BIT 7
877  #define RTE_SSP1_SCK_FUNC 2
878 #elif (RTE_SSP1_SCK_PIN_SEL == 1)
879  #define RTE_SSP1_SCK_PORT 1
880  #define RTE_SSP1_SCK_BIT 31
881  #define RTE_SSP1_SCK_FUNC 2
882 #else
883  #error "Invalid SSP1 SSP1_SCK Pin Configuration!"
884 #endif
885 
886 // <o> SSP1_MISO <0=>Not used <1=>P0_8
887 // <i> Master In Slave Out for SSP1
888 #define RTE_SSP1_MISO_PIN_SEL 1
889 #if (RTE_SSP1_MISO_PIN_SEL == 0)
890  #define RTE_SSP1_MISO_PIN_EN 0
891 #elif (RTE_SSP1_MISO_PIN_SEL == 1)
892  #define RTE_SSP1_MISO_PORT 0
893  #define RTE_SSP1_MISO_BIT 8
894  #define RTE_SSP1_MISO_FUNC 2
895 #else
896  #error "Invalid SSP1 SSP1_MISO Pin Configuration!"
897 #endif
898 #ifndef RTE_SSP1_MISO_PIN_EN
899 #define RTE_SSP1_MISO_PIN_EN 1
900 #endif
901 
902 // <o> SSP1_MOSI <0=>Not used <1=>P0_9
903 // <i> Master Out Slave In for SSP1
904 #define RTE_SSP1_MOSI_PIN_SEL 1
905 #if (RTE_SSP1_MOSI_PIN_SEL == 0)
906  #define RTE_SSP1_MOSI_PIN_EN 0
907 #elif (RTE_SSP1_MOSI_PIN_SEL == 1)
908  #define RTE_SSP1_MOSI_PORT 0
909  #define RTE_SSP1_MOSI_BIT 9
910  #define RTE_SSP1_MOSI_FUNC 2
911 #else
912  #error "Invalid SSP1 SSP1_MOSI Pin Configuration!"
913 #endif
914 #ifndef RTE_SSP1_MOSI_PIN_EN
915 #define RTE_SSP1_MOSI_PIN_EN 1
916 #endif
917 
918 // </h>
919 // <h> DMA
920 // <e> Tx
921 // <o1> Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
922 // </e>
923 #define RTE_SSP1_DMA_TX_EN 0
924 #define RTE_SSP1_DMA_TX_CH 2
925 // <e> Rx
926 // <o1> Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
927 // </e>
928 #define RTE_SSP1_DMA_RX_EN 0
929 #define RTE_SSP1_DMA_RX_CH 3
930 // </h> DMA
931 // </e>
932 
933 
934 // <e> SPI (Serial Peripheral Interface) [Driver_SPI2]
935 // <i> Configuration settings for Driver_SPI2 in component ::Drivers:SPI
936 #define RTE_SPI 1
937 
938 // <h> Pin Configuration
939 // <o> SPI_SSEL <0=>Not used <1=>P0_16
940 // <i> Slave Select for SPI
941 #define RTE_SPI_SSEL_PIN_SEL 1
942 #if (RTE_SPI_SSEL_PIN_SEL == 0)
943 #define RTE_SPI_SSEL_PIN_EN 0
944 #elif (RTE_SPI_SSEL_PIN_SEL == 1)
945  #define RTE_SPI_SSEL_PORT 0
946  #define RTE_SPI_SSEL_BIT 16
947  #define RTE_SPI_SSEL_FUNC 3
948 #else
949  #error "Invalid SPI SPI_SSEL Pin Configuration!"
950 #endif
951 #ifndef RTE_SPI_SSEL_PIN_EN
952 #define RTE_SPI_SSEL_PIN_EN 1
953 #endif
954 // <o> SPI_SCK <0=>P0_15
955 // <i> Serial clock for SPI
956 #define RTE_SPI_SCK_PIN_SEL 0
957 #if (RTE_SPI_SCK_PIN_SEL == 0)
958  #define RTE_SPI_SCK_PORT 0
959  #define RTE_SPI_SCK_BIT 15
960  #define RTE_SPI_SCK_FUNC 3
961 #else
962  #error "Invalid SPI SPI_SCK Pin Configuration!"
963 #endif
964 // <o> SPI_MISO <0=>Not used <1=>P0_17
965 // <i> Master In Slave Out for SPI
966 #define RTE_SPI_MISO_PIN_SEL 1
967 #if (RTE_SPI_MISO_PIN_SEL == 0)
968  #define RTE_SPI_MISO_PIN_EN 0
969 #elif (RTE_SPI_MISO_PIN_SEL == 1)
970  #define RTE_SPI_MISO_PORT 0
971  #define RTE_SPI_MISO_BIT 17
972  #define RTE_SPI_MISO_FUNC 3
973 #else
974  #error "Invalid SPI SPI_MISO Pin Configuration!"
975 #endif
976 #ifndef RTE_SPI_MISO_PIN_EN
977 #define RTE_SPI_MISO_PIN_EN 1
978 #endif
979 
980 // <o> SPI_MOSI <0=>Not used <1=>P0_18
981 // <i> Master Out Slave In for SPI
982 #define RTE_SPI_MOSI_PIN_SEL 1
983 #if (RTE_SPI_MOSI_PIN_SEL == 0)
984  #define RTE_SPI_MOSI_PIN_EN 0
985 #elif (RTE_SPI_MOSI_PIN_SEL == 1)
986  #define RTE_SPI_MOSI_PORT 0
987  #define RTE_SPI_MOSI_BIT 18
988  #define RTE_SPI_MOSI_FUNC 3
989 #else
990  #error "Invalid SPI SPI_MOSI Pin Configuration!"
991 #endif
992 #ifndef RTE_SPI_MOSI_PIN_EN
993 #define RTE_SPI_MOSI_PIN_EN 1
994 #endif
995 
996 // </h> Pin Configuration
997 // </e> SPI (Serial Peripheral Interface) [Driver_SPI2]
998 
999 
1000 // <e> I2S0 (Integrated Interchip Sound 0) [Driver_SAI0]
1001 // <i> Configuration settings for Driver_SAI0 in component ::Drivers:SAI
1002 #define RTE_I2S0 0
1003 
1004 // <h> Pin Configuration
1005 // <o> I2S0_RX_SCK <0=>Not used <1=>P0_4 <2=>P0_23
1006 // <i> Receive clock for I2S0
1007 #define RTE_I2S0_RX_SCK_PIN_SEL 1
1008 #if (RTE_I2S0_RX_SCK_PIN_SEL == 0)
1009 #define RTE_I2S0_RX_SCK_PIN_EN 0
1010 #elif (RTE_I2S0_RX_SCK_PIN_SEL == 1)
1011  #define RTE_I2S0_RX_SCK_PORT 0
1012  #define RTE_I2S0_RX_SCK_BIT 4
1013  #define RTE_I2S0_RX_SCK_FUNC 1
1014 #elif (RTE_I2S0_RX_SCK_PIN_SEL == 2)
1015  #define RTE_I2S0_RX_SCK_PORT 0
1016  #define RTE_I2S0_RX_SCK_BIT 23
1017  #define RTE_I2S0_RX_SCK_FUNC 2
1018 #else
1019  #error "Invalid I2S0 I2S0_RX_SCK Pin Configuration!"
1020 #endif
1021 #ifndef RTE_I2S0_RX_SCK_PIN_EN
1022 #define RTE_I2S0_RX_SCK_PIN_EN 1
1023 #endif
1024 // <o> I2S0_RX_WS <0=>Not used <1=>P0_5 <2=>P0_24
1025 // <i> Receive word select for I2S0
1026 #define RTE_I2S0_RX_WS_PIN_SEL 1
1027 #if (RTE_I2S0_RX_WS_PIN_SEL == 0)
1028 #define RTE_I2S0_RX_WS_PIN_EN 0
1029 #elif (RTE_I2S0_RX_WS_PIN_SEL == 1)
1030  #define RTE_I2S0_RX_WS_PORT 0
1031  #define RTE_I2S0_RX_WS_BIT 5
1032  #define RTE_I2S0_RX_WS_FUNC 1
1033 #elif (RTE_I2S0_RX_WS_PIN_SEL == 2)
1034  #define RTE_I2S0_RX_WS_PORT 0
1035  #define RTE_I2S0_RX_WS_BIT 24
1036  #define RTE_I2S0_RX_WS_FUNC 2
1037 #else
1038  #error "Invalid I2S0 I2S0_RX_WS Pin Configuration!"
1039 #endif
1040 #ifndef RTE_I2S0_RX_WS_PIN_EN
1041 #define RTE_I2S0_RX_WS_PIN_EN 1
1042 #endif
1043 // <o> I2S0_RX_SDA <0=>Not used <1=>P0_6 <2=>P0_25
1044 // <i> Receive master clock for I2S0
1045 #define RTE_I2S0_RX_SDA_PIN_SEL 1
1046 #if (RTE_I2S0_RX_SDA_PIN_SEL == 0)
1047 #define RTE_I2S0_RX_SDA_PIN_EN 0
1048 #elif (RTE_I2S0_RX_SDA_PIN_SEL == 1)
1049  #define RTE_I2S0_RX_SDA_PORT 0
1050  #define RTE_I2S0_RX_SDA_BIT 6
1051  #define RTE_I2S0_RX_SDA_FUNC 1
1052 #elif (RTE_I2S0_RX_SDA_PIN_SEL == 2)
1053  #define RTE_I2S0_RX_SDA_PORT 0
1054  #define RTE_I2S0_RX_SDA_BIT 25
1055  #define RTE_I2S0_RX_SDA_FUNC 2
1056 #else
1057  #error "Invalid I2S0 I2S0_RX_SDA Pin Configuration!"
1058 #endif
1059 #ifndef RTE_I2S0_RX_SDA_PIN_EN
1060 #define RTE_I2S0_RX_SDA_PIN_EN 1
1061 #endif
1062 // <o> I2S0_RX_MCLK <0=>Not used <1=>P4_28
1063 // <i> Receive master clock for I2S0
1064 #define RTE_I2S0_RX_MCLK_PIN_SEL 0
1065 #if (RTE_I2S0_RX_MCLK_PIN_SEL == 0)
1066 #define RTE_I2S0_RX_MCLK_PIN_EN 0
1067 #elif (RTE_I2S0_RX_MCLK_PIN_SEL == 1)
1068  #define RTE_I2S0_RX_MCLK_PORT 4
1069  #define RTE_I2S0_RX_MCLK_BIT 28
1070  #define RTE_I2S0_RX_MCLK_FUNC 1
1071 #else
1072  #error "Invalid I2S0 I2S0_RX_MCLK Pin Configuration!"
1073 #endif
1074 #ifndef RTE_I2S0_RX_MCLK_PIN_EN
1075 #define RTE_I2S0_RX_MCLK_PIN_EN 1
1076 #endif
1077 // <o> I2S0_TX_SCK <0=>Not used <1=>P0_7 <2=>P2_11
1078 // <i> Transmit clock for I2S0
1079 #define RTE_I2S0_TX_SCK_PIN_SEL 1
1080 #if (RTE_I2S0_TX_SCK_PIN_SEL == 0)
1081 #define RTE_I2S0_TX_SCK_PIN_EN 0
1082 #elif (RTE_I2S0_TX_SCK_PIN_SEL == 1)
1083  #define RTE_I2S0_TX_SCK_PORT 0
1084  #define RTE_I2S0_TX_SCK_BIT 7
1085  #define RTE_I2S0_TX_SCK_FUNC 1
1086 #elif (RTE_I2S0_TX_SCK_PIN_SEL == 2)
1087  #define RTE_I2S0_TX_SCK_PORT 2
1088  #define RTE_I2S0_TX_SCK_BIT 11
1089  #define RTE_I2S0_TX_SCK_FUNC 3
1090 #else
1091  #error "Invalid I2S0 I2S0_TX_SCK Pin Configuration!"
1092 #endif
1093 #ifndef RTE_I2S0_TX_SCK_PIN_EN
1094 #define RTE_I2S0_TX_SCK_PIN_EN 1
1095 #endif
1096 // <o> I2S0_TX_WS <0=>Not used <1=>P0_8 <2=>P2_12
1097 // <i> Transmit word select for I2S0
1098 #define RTE_I2S0_TX_WS_PIN_SEL 1
1099 #if (RTE_I2S0_TX_WS_PIN_SEL == 0)
1100 #define RTE_I2S0_TX_WS_PIN_EN 0
1101 #elif (RTE_I2S0_TX_WS_PIN_SEL == 1)
1102  #define RTE_I2S0_TX_WS_PORT 0
1103  #define RTE_I2S0_TX_WS_BIT 8
1104  #define RTE_I2S0_TX_WS_FUNC 1
1105 #elif (RTE_I2S0_TX_WS_PIN_SEL == 2)
1106  #define RTE_I2S0_TX_WS_PORT 2
1107  #define RTE_I2S0_TX_WS_BIT 12
1108  #define RTE_I2S0_TX_WS_FUNC 3
1109 #else
1110  #error "Invalid I2S0 I2S0_TX_WS Pin Configuration!"
1111 #endif
1112 #ifndef RTE_I2S0_TX_WS_PIN_EN
1113 #define RTE_I2S0_TX_WS_PIN_EN 1
1114 #endif
1115 // <o> I2S0_TX_SDA <0=>Not used <1=>P0_9 <2=>P2_13
1116 // <i> Transmit data for I2S0
1117 #define RTE_I2S0_TX_SDA_PIN_SEL 1
1118 #if (RTE_I2S0_TX_SDA_PIN_SEL == 0)
1119 #define RTE_I2S0_TX_SDA_PIN_EN 0
1120 #elif (RTE_I2S0_TX_SDA_PIN_SEL == 1)
1121  #define RTE_I2S0_TX_SDA_PORT 0
1122  #define RTE_I2S0_TX_SDA_BIT 9
1123  #define RTE_I2S0_TX_SDA_FUNC 1
1124 #elif (RTE_I2S0_TX_SDA_PIN_SEL == 2)
1125  #define RTE_I2S0_TX_SDA_PORT 2
1126  #define RTE_I2S0_TX_SDA_BIT 13
1127  #define RTE_I2S0_TX_SDA_FUNC 3
1128 #else
1129  #error "Invalid I2S0 I2S0_TX_SDA Pin Configuration!"
1130 #endif
1131 #ifndef RTE_I2S0_TX_SDA_PIN_EN
1132 #define RTE_I2S0_TX_SDA_PIN_EN 1
1133 #endif
1134 // <o> I2S0_TX_MCLK <0=>Not used <1=>P4_29
1135 // <i> Transmit master clock for I2S0
1136 #define RTE_I2S0_TX_MCLK_PIN_SEL 1
1137 #if (RTE_I2S0_TX_MCLK_PIN_SEL == 0)
1138 #define RTE_I2S0_TX_MCLK_PIN_EN 0
1139 #elif (RTE_I2S0_TX_MCLK_PIN_SEL == 1)
1140  #define RTE_I2S0_TX_MCLK_PORT 4
1141  #define RTE_I2S0_TX_MCLK_BIT 29
1142  #define RTE_I2S0_TX_MCLK_FUNC 1
1143 #else
1144  #error "Invalid I2S0 I2S0_TX_MCLK Pin Configuration!"
1145 #endif
1146 #ifndef RTE_I2S0_TX_MCLK_PIN_EN
1147 #define RTE_I2S0_TX_MCLK_PIN_EN 1
1148 #endif
1149 // </h> Pin Configuration
1150 
1151 // <h> DMA
1152 // <e> Tx
1153 // <o1> Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
1154 // <o2> Peripheral <0=>9 (DMAMUXPER9)
1155 // </e>
1156 #define RTE_I2S0_DMA_TX_EN 1
1157 #define RTE_I2S0_DMA_TX_CH 0
1158 // <e> Rx
1159 // <o1> Channel <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
1160 // <o2> Peripheral <0=>10 (DMAMUXPER10)
1161 // </e>
1162 #define RTE_I2S0_DMA_RX_EN 1
1163 #define RTE_I2S0_DMA_RX_CH 1
1164 // </h> DMA
1165 // </e> I2S0 (Integrated Interchip Sound 0) [Driver_SAI0]
1166 
1167 #endif /* __RTE_DEVICE_H */